BIST造句怎么写

Board-level Interconnect Test and BIST Implementation in Boundary Scan Environment

Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.

Research of I_(DDT) ATPG Algorithm Based on Ambiguous Delay Assignments and BIST Test Pattern Generator Design;

实践*,该测试框架有利于BIST软件测试思想的进一步研究和实现。

为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。

Keywords: Low power testing, BIST.

One Example of High Performance Memory BIST Design;

Study on Mixed-signal BIST Based on Pseudo-random Testing;

The Study on Built-in Self-test (BIST) for Integrated Circuits Based-on Multiple Scan Chains;

This work will be greatly conductive to further study and the realization of BIST software test idea.

在分析全扫描内建自测试(BIST)过高测试功耗原因的基础上，提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗BIST。

The Research on Logic BIST of SOC;

Application of BIST in SoC Based Embedded Microprocessor Core

Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.

BIST-Based Delay-Fault Testing in Dynamic Reconfiguration FPGAs

另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。

Research on Low Power Deterministic BIST Based on Genetic Algorithm-Folding Counter